1. Field of the Invention
The present invention relates to facilitation of a test for a semiconductor device (for example, an LSI).
2. Description of the Background Art
A test for a semiconductor device according to the prior art will be described with reference to FIGS. 19 to 21. FIG. 19 shows a large number of semiconductor devices formed on a wafer 1. The reference numeral 20 denotes a principal plane of a semiconductor substrate of the semiconductor device, and the reference numeral 3 denotes a large. number of pads which are provided on the principal plane 20 of the semiconductor substrate and are conducted to a circuit (not shown) formed on the principal plane 20 of the semiconductor substrate. FIG. 20 shows a probe card 4 (test jig) which is attached to a tester (not shown) and has a probe needle 5 provided thereon. FIG. 21 shows a state in which the probe card 4 of FIG. 20 is in contact with the semiconductor device of FIG. 19.
The test for the semiconductor device includes a function test and a DC test.
The function test is performed by causing the probe needle 5 to come in contact with all the pads 3 provided in the semiconductor device in FIG. 21. In this test, the function of the semiconductor device is inspected.
For example, DC tests other than an output voltage test such as a test for a leak current flowing into a pad to be tested (a test object pad) and a contact test (a conduction test) for the test object pad can be performed by causing the probe needle 5 to come in contact with a power pad and a GND (ground) pad for driving the semiconductor device and the test object pad.
The output voltage test can be performed by causing the probe needle 5 to come in contact with the power pad, the GND pad, the test object pad and a pad (setting pad) for setting a state of the test object pad. In this specification, for example, the output voltage test includes a test (a VOH test or a VOL test) for checking a voltage which is actually output from the test object pad in a state in which the semiconductor device is operated by the setting pad to output an xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d level from the test object pad, a test (an HI-Z test) for deciding whether or not the test object pad is set to have a desired high impedance by the operation of the semiconductor device with the use of the setting pad, and the like.
According to a technique shown in FIG. 21, the function test and all the DC tests including the output voltage test can be performed. However, the probe needle 5 is caused to come in contact with all the pads 3. For this reason, the probe card 4 having the same number of probe needles 5 as the number of pads 3 is required. As a technique in which a test for a semiconductor device having a large number of pads 3 can be performed by the probe card 4 having a small number of probe needles 5, a boundary scan test has been known.
A test for a semiconductor device using boundary scan according to the prior art will be described with reference to FIGS. 22, 23, 24a, 24b, 24c and 24d. FIGS. 22, 23, 24a, 24b, 24c and 24d correspond to FIGS. 19 to 21, respectively. In FIG. 22, the reference numeral 3a denotes a pad for supplying power to the semiconductor device, the reference numeral 3b denotes a pad for supplying a GND to the semiconductor device, TCLK denotes a pad for inputting a clock signal, TMS denotes a pad for setting a test mode, TDI denotes a pad for inputting serial data, and TDO denotes a pad for outputting the serial data.
The pads 3a and 3b form a set of driving pads 3ab for supplying a driving voltage of the semiconductor device. The pads TCLK, TMS, TDI and TDO form a set of boundary scanning pads BSP for performing the boundary scan test.
A large number of pads provided on the principal plane 20 of the semiconductor substrate are generally referred to as the pads 3. The pads 3 include the boundary scanning pads BSP and the driving pads 3ab. 
The boundary scanning pads BSP are not always formed by these four kinds of pads. In some cases, a pad which serves to reset a circuit for performing the boundary scan on an inside of the semiconductor device or the like is added to the boundary scanning pads BSP.
Furthermore, a plurality of pads arranged along a side of the principal plane 20 of the semiconductor substrate is referred to as a pad string.
For the boundary scan, it is sufficient that the probe needle 5 comes in contact with the pads 3a and 3b and the boundary scanning pads BSP. Therefore, even if a small number of probe needles 5 are provided, the function test can be performed.
As shown in FIG. 22, the adjacent pads 3 are provided with an equal space (pad pitch), all the pads forming the boundary scanning pads BSP are included in one pad string of the principal plane 20 of the semiconductor substrate, the pads 3a and 3b are included in each pad string of the principal plane 20 of the semiconductor substrate, and the probe needle 5 is not provided on the probe card 4 corresponding to all the pads 3 of the principal plane 20 of the semiconductor substrate but is provided in only a portion corresponding to one pad string of the principal plane 20 of the semiconductor substrate as shown in FIG. 23. With such structures of the principal plane 20 of the semiconductor substrate and the probe card 4, any of four pad strings of the principal plane 20 of the semiconductor substrate which includes the boundary scanning pads BSP is first caused to come in contact with the probe needle 5 so that the function test and the DC test including the output voltage test for each pad 3 with which the probe needle 5 is in contact can be performed (FIG. 24a), and the principal plane 20 of the semiconductor substrate is then rotated by 90 degrees so that the DC tests other than the output voltage test for each pad 3 can be performed for three residual pad strings (FIGS. 24b to 24d).
Referring to FIGS. 24b, 24c and 24d, however, the probe needle 5 does not come in contact with the boundary scanning pads BSP. Therefore, the output voltage test using the boundary scanning pads BSP as setting pads cannot be performed for the three residual pad strings. Consequently, the test is incompletely performed.
A first aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate provided with a boundary scan test circuit having an I/O pad selecting function, and a large number of pads provided on a principal plane of the semiconductor substrate and conducted to a boundary scan test circuit having the I/O pad selecting function, the principal plane of the semiconductor substrate having a plurality of areas with which a test jig comes in contact, the pads including at least one set of driving pads for supplying a driving voltage of the semiconductor device, and at least one set of boundary scanning pads for performing a boundary scan test, and the at least one set of driving pads and the at least one set of boundary scanning pads being placed in positions where the test jig can come in contact with any of the areas.
A second aspect of the present invention is directed to the semiconductor device, wherein plural sets of driving pads are provided corresponding to the areas and are included in the respective areas, and plural sets of boundary scanning pads are provided corresponding to the areas and are included in the respective areas.
A third aspect of the present invention is directed to the semiconductor device, wherein the pads included in each of the areas are arranged along a side of the principal plane of the semiconductor substrate.
A fourth aspect of the present invention is directed to the semiconductor device, wherein the areas have a common region to be used for all of them in common, and the one set of boundary scanning pads are included in the common region.
A fifth aspect of the present invention is directed to the semiconductor device, wherein the areas are four areas obtained by virtually dividing the principal plane of the semiconductor substrate by two orthogonal segments, the common region includes a region on the two orthogonal segments, and the one set of boundary scanning pads is placed in positions on the two orthogonal segments at equal distances from an intersection of the two orthogonal segments.
A sixth aspect of the present invention is directed to the semiconductor device, wherein the common region further includes at least one region on two other orthogonal segments whose intersection is positioned on the intersection of the two orthogonal segments, and the at least one set of driving pads is placed in positions on the other two orthogonal segments at equal distances from the intersection.
A seventh aspect of the present invention is directed to the semiconductor device, wherein the areas are two areas obtained by virtually dividing the principal plane of the semiconductor substrate by one segment, and the common region includes a region on the one segment.
An eighth aspect of the present invention is directed to the semiconductor device, wherein the one set of boundary scanning pads is placed on the one segment which is symmetrical with respect to a predetermined point on the one segment.
A ninth aspect of the present invention is directed to the semiconductor device, wherein the areas are two areas obtained by virtually dividing the principal plane of the semiconductor substrate by one segment, the common region includes a region on two orthogonal segments whose intersection is positioned on the one segment, and the one set of boundary scanning pads is placed in positions on the two orthogonal segments at equal distances from the intersection of the two orthogonal segments.
A tenth aspect of the present invention is directed to the semiconductor device, wherein the at least one set of driving pads is included in the common region.
An eleventh aspect of the present invention is directed to the semiconductor device, wherein the plural sets of boundary scanning pads are placed in identical positions in the areas.
A twelfth aspect of the present invention is directed to the semiconductor device, wherein plural sets of driving pads are provided corresponding to the areas, and are included in the respective areas, and the plural sets of driving pads are placed in identical positions in the areas.
A thirteenth aspect of the present invention is directed to the semiconductor device, wherein the boundary scan test circuit having an I/O pad selecting function includes a boundary scanning circuit for performing the boundary scan, and a selector for conducting, to the boundary scanning circuit, any of the plural sets of boundary scanning pads with which the test jig is in contact.
A fourteenth aspect of the present invention is directed to the semiconductor device, wherein one pad included in the one set of boundary scanning pads is placed on the intersection.
A fifteenth aspect of the present invention is directed to the semiconductor device, wherein the pads further include a dummy pad for making arrangements of the pads identical to each other in the areas.
According to the first aspect of the present invention, the test jig is in contact with the driving pads and the boundary scanning pads in the test for each area. Therefore, a function test and a DC test including an output voltage test can be performed completely.
According to the second aspect of the present invention, the driving pads and the boundary scanning pads are included in the respective areas so that the first aspect of the present invention can be realized.
According to the third aspect of the present invention, the present invention can be applied to a semiconductor device in which a principal plane of a semiconductor substrate is a quadrilateral and pads are arranged on a straight line along a side of the principal plane of the semiconductor substrate, for example.
According to the fourth aspect of the present invention, a set of boundary scanning pads is included in the common region. Consequently, it is sufficient that a set of boundary scanning pads is provided on the principal plane of the semiconductor substrate. Thus, the number of the boundary scanning pads can be reduced.
According to the fifth aspect of the present invention, the arrangement of the boundary scanning pads is not changed before and after the principal plane of the semiconductor substrate is rotated by 90 degrees around the intersection of the two orthogonal segments. Therefore, the principal plane of the semiconductor substrate is rotated by 90 degrees around the intersection so that the test jig can be caused to come in contact with the boundary scanning pads in the test, for example.
According to the sixth aspect of the present invention, the arrangement of the pads is not changed before and after the principal plane of the semiconductor substrate is rotated by 90 degrees around the intersection of the two orthogonal segments and the driving pads can be placed on other two orthogonal segments. Therefore, the present invention is effective in a case where the boundary scanning pads and the driving pads cannot be placed on a set of two orthogonal segments.
According to the seventh aspect of the present invention, the principal plane of the semiconductor substrate is moved from one of the areas toward other areas so that the test jig can be caused to come in contact with the boundary scanning pads in the test, for example.
According to the eighth aspect of the present invention, the arrangement of the boundary scanning pads is not changed before and after the principal plane of the semiconductor substrate is rotated by 180 degrees around a certain point on one segment. Therefore, the principal plane of the semiconductor substrate is rotated by 180 degrees around the certain point so that the test jig can be caused to come in contact with the boundary scanning pads in the test, for example.
According to the ninth aspect of the present invention, the arrangement of the boundary scanning pads is not changed before and after the principal plane of the semiconductor substrate is rotated by 180 degrees around the intersection of the two orthogonal segments. Therefore, the principal plane of the semiconductor substrate is rotated by 180 degrees around the intersection so that the test jig can be caused to come in contact with the boundary scanning pads in the test, for example.
According to the tenth aspect of the present invention, the number of the driving pads can be reduced.
According to the eleventh aspect of the present invention, a part of a program can be shared in the test for each area. Therefore, development man-days of the program can be reduced.
According to the twelfth aspect of the present invention, the test jig can cope with a semiconductor device which requires greater power.
According to the thirteenth aspect of the present invention, input and output of a probing boundary scanning pads can be made effective.
According to the fourteenth aspect of the present invention, even if one set of boundary scanning pads includes five pads, for example, one of them is placed on the intersection so that the arrangement of the boundary scanning pads is not changed before and after the principal plane of the semiconductor substrate is rotated by 90 degrees around the intersection.
According to the fifteenth aspect of the present invention, the test jig can be prevented from damaging the principal plane of the semiconductor substrate other than the pads.
In order to solve the above-mentioned problem, it is an object of the present invention to provide a semiconductor device capable of performing an output voltage test for all I/O pads and output pads by using a probe card having probe needles whose number is smaller than that of the pads of the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.